1. Field of the Invention
The present invention relates to a nonvolatile memory controller for controlling a nonvolatile memory such as a flash memory, and to a nonvolatile storage device using such nonvolatile memory controller.
2. Description of the Related Art
In recent years, as a nonvolatile storage device equipped with a NAND-type flash memory as a rewritable nonvolatile memory, memory cards are being used as the storage medium of digital cameras and mobile phones, and its market is expanding.
Moreover, pursuant to the microfabrication of the semiconductor process, the bit unit price of nonvolatile storage devices has decreased and nonvolatile storage devices are being used as an inexpensive storage device in markets other than memory cards; for example, as memories of SSD (Solid State Drive) used as a substitute of HDD (Hard Disk Drive) or of embedded systems which are directly mounted on a host device, and its application is expanding.
Here, the characteristics of a NAND-type flash memory can be listed as follows:                A nonvolatile memory with the largest capacity among the semiconductor memories and with a low bit cost        The reliability of data is deterioration pursuant to the microfabrication of the semiconductor process        There are a plurality of types of memory cells including binary and multi-valued        
Each of these characteristics is now explained in order.
With a NAND-type flash memory, if the minimum feature size of the semiconductor process is F, then one memory cell can be configured in a size of the square of (2F). This is why the NAND-type flash memory has the lowest bit cost and largest capacity among the semiconductor memories.
Moreover, in recent years, a NAND-type flash memory is being manufactured by using, as the process driver, the most advanced process rule of the semiconductor process. Consequently, a NAND-type flash memory is now being used in systems that use different memories.
For example, a system in which a program code demanded of high-speed random access is stored in a NOR-type flash memory and user data demanded of large capacity is stored in a NAND-type flash memory is being replaced only with a single NAND-type flash memory.
This is because the capacity of the mounted NAND-type flash memory is sufficiently smaller than the capacity of the required NOR-type flash memory and, even if the program code loaded in the NOR-type flash memory is stored in the NAND-type flash memory, the influence is minimal, and the cost advantages of being able to eliminate the NOR-type flash memory are higher even if it is necessary to apply creative efforts in using the NAND-type flash memory.
Moreover, the increase in capacity of the NAND-type flash memory depends largely on the microfabrication of the semiconductor process. Nevertheless, the microfabrication of the semiconductor process is not only advantageous, it also entails the problem of deteriorating the reliability of data. Specifically, pursuant to the advancement of microfabrication, the data retention characteristics will deteriorate, and degradation of characteristics due to the rewrite processing will advance.
Here, a memory cell of the flash memory takes on a configuration of retaining, in a nonvolatile manner, electrons between a control gate and a substrate in a MOS (Metal Oxide Semiconductor)-type transistor, and performs the erasure and writing of data by shifting the electrons between the substrate and the floating gate. Moreover, data is read from the memory cell of the flash memory by determining the amount of current that flows through the transistor configuring the flash memory.
As described above, when the erasure and writing of data are repeated to the memory cells of the flash memory, the electrons move between the substrate and the floating gate, and this causes the degradation of the insulator film (hereinafter referred to as the “gate insulator film”) between the substrate and the floating gate. When the gate insulator film becomes degraded, electrons are leaked from the floating gate to the substrate via the defects existing in the gate insulator film, the writing efficiency deteriorates due to the influence of the electrons trapped in the defects of the gate insulator film, and this consequently deteriorates the reliability of data.
Even with the foregoing disadvantages, with the unparalleled bit unit price as its strength, the use of flash memories manufactured based on microfabrication is expanding even if it is necessary to apply creative efforts for improving the reliability of data.
Moreover, an important element upon examining the reliability of data of a flash memory is the handling of memory cells in the writing of data. Specifically, the reliability of data differs considerably depending on whether data is written as a binary memory cell or data is written as a multi-valued memory cell, and the reliability of data is higher if data is written as a binary memory cell. Meanwhile, needless to say, the capacity of the memory can be increased if data is written as a multi-valued memory cell, and the bit unit price can be reduced at the same time.
From the foregoing characteristics of a NAND-type flash memory, there are cases of using a plurality of different writing methods upon storing data in the flash memory. For example, it is possible to perform binary writing upon writing a program code demanded of high reliability as a binary memory cell, and perform multi-valued writing upon writing user data demanded of high capacity as a multi-valued memory cell.
The binary writing and the multi-valued writing are now compared. In order to simply the explanation, the case of performing binary writing and the case of performing four-valued writing are now explained with reference to the drawings.
FIG. 12 is a diagram showing how the threshold voltage of the memory cells is distributed in the case of binary writing. The distribution on the left side of FIG. 12 shows the distribution of the threshold voltage of the memory cells in an erased state, and the distribution on the right side of FIG. 12 shows the distribution of the threshold voltage of the memory cells in a written state. In the case of binary writing, 1 bit of information is stored depending on whether the threshold voltage of the memory cell is on the left-side distribution or the right-side distribution.
FIG. 13 is a diagram showing how the threshold voltage of the memory cells is distributed in the case of four-valued writing. The distribution on the left side of FIG. 13 shows the distribution of the threshold voltage of the memory cells in an erased state, and the three distributions on the right side of FIG. 13 respectively show the distribution of the threshold voltage of the memory cells in respectively different written states. In the case of four-valued writing, 2 bit information is stored depending on where the threshold voltage of the memory cells is located among the four distributions.
As evident from FIG. 12 and FIG. 13, the distribution interval 1301 of the threshold voltage in the case of four-valued writing is narrower in comparison to the distribution interval 1201 of the threshold voltage in the case of binary writing. Accordingly, as the distribution interval becomes narrow, the margin relative to the variation in the threshold voltage of the memory cells becomes small. In other words, the data retention period is shorter with the four-valued writing in comparison to the binary writing.
Moreover, the distribution width 1302 of the threshold voltage in the case of four-valued writing needs to be narrower in comparison to the distribution width 1202 of the threshold voltage in the case of binary writing. Accordingly, in order to narrow the distribution of the threshold voltage of the memory cells, it is necessary to repeatedly execute detailed control in the writing to the memory cells. Consequently, degradation of the gate insulator film during the rewriting process will advance as a result of the number of times that writing stress is applied to the memory cells increasing, or the application period becoming longer, and the rewrite cycle will decrease.
FIG. 14 is a diagram showing how the threshold voltage of the memory cells is distributed in the case of eight-valued writing. In the case of eight-valued writing, it is evident that the distribution interval 1401 of the threshold voltage and the distribution voltage 1402 of the threshold voltage are respectively even narrower in comparison to the case of four-valued writing. In other words, if the eight-valued writing is performed, the rewrite cycle will decrease further, and the data retention period will be shortened further.
Moreover, Japanese Patent Application Publication No. 2008-257773 describes technology related to a nonvolatile storage device with a binary writing area and a multi-valued writing area, wherein, by physically dividing and managing a memory cell array into an area to use as the binary writing area and an area for use as the sixteen-valued (i.e., multi-valued) writing area, optimal block management in the respective areas is performed.
Nevertheless, with the configuration described in foregoing Japanese Patent Application Publication No. 2008-257773, since the area used as the binary writing area and the area used as the sixteen-valued writing area are physically divided and managed, if only the binary writing area is repeated used, while the rewrite cycle of the physical blocks of the binary writing area will increase and become degraded, the physical blocks of the multi-valued writing area will not degrade since they are not used, and, consequently, there is a problem in that the overall physical blocks cannot be used uniformly.
Moreover, the degradation level of the respective areas is managed only based on the rewrite cycle. Thus, since only a common degradation scale is available for both binary writing and sixteen-valued writing which have different degradation levels to begin with, this becomes a factor in inhibiting the mutual exploitation of the respective areas.